ds2223/ds2224 econoram ds2223/ds2224 080598 1/10 features ? lowcost, generalpurpose, 256bit memory ds2223 has 256bit sram ds2224 has 32bit rom, 224bit sram ? reduces control, address and data interface to a single pin ? each ds2224 32bit rom is factorylasered with a unique serial number ? ds2224 portion of rom with custom code and unique serial number available ? minimal operating power: 45 nanocoulombs per transaction @1.5v typical ? less than 15 na standby current at 25 c ? nonvolatile data retention easily achieved via low cost alkaline batteries or capacitors ? directly connects to a port pin of popular microcontrol-lers ? operation from 1.2 to 5.5 volts ? popular to92 or sot223 surface mount package ? operates over industrial temperature range 40 c to +85 c description the ds2223 and ds2224 econorams are fully static, micropowered, read/write memories in lowcost to92 or sot223 packages. the ds2223 is orga- nized as a serial 256 x 1 bit static read/write memory. the ds2224's first 32 bits are lasered with a unique id code at the time of manufacture; the remaining 224 bits are static read/write memory. signaling necessary for reading or writing is reduced to just one interface lead. both the ds2223 and ds2224 are not recommended for new designs. however, the parts will remain avail- able until the year 2003, at least. package outline 12 3 1 23 1 23 4 sot223 top view bottom view to92 see mech. drawings section see mech. drawings section pin connections pin 1 gnd ground pin 2 dq data in/out pin 3 v cc supply pin 4 gnd ground ordering information ds2223 256bit sram to92 package ds2223z 256bit sram sot223 package ds2223t 1000 piece tapeandreel of ds2223 ds2223y 2500 piece tapeandreel of ds2223z ds2224 32bit serial number (rom), 224bit sram to92 package ds2224z 32bit serial number (rom), 224bit sram sot223 package ds2224t 1000 piece tapeandreel of ds2224 ds2224y 2500 piece tapeandreel of ds2224z downloaded from: http:///
ds2223/ds2224 080598 2/10 operation all communications to and from the econoram are accomplished via a single interface lead. econoram data is read and written through the use of time slots. all data is preceded by a command byte to specify the type of transaction. once a specific transaction has been initiated, either a read or a write, it must be com- pleted for all memory locations before another transaction can be started. 1wire signalling the econoram requires strict protocols to insure data integrity. the protocol consists of three types of signal- ling on one line: write 0 time slot, write 1 time slot and read data time slot. all these signals are initiated by the host. read/write time slots the definitions of write and read time slots are illustrated in figures 1 through 3. all time slots are initiated by the host driving the data line low. the falling edge of the data line synchronizes the econoram to the host by trigger- ing a delay circuit in the econoram. during write time slots, the delay circuit determines when the econoram will sample the data line. for a read data time slot, if a a0o is to be transmitted, the delay circuit determines how long the econoram will hold the data line low overriding the 1 generated by the host. if the data bit is a a1o, the econoram will leave the read data time slot unchanged. command byte the command byte to specify the type of transaction is transmitted lsb first from the host to the econoram using write time slots. the first bit of the command byte (see figure 4) is a logic 1. this indicates to the econo- ram that a command byte is being written. the next two bits are the select bits which denote the physical address of the econoram that is to be accessed (set to 00 currently). the remaining five bits determine whether a read or a write operation is to follow. if a write operation is to be performed, all five bits are set to a logic 1 level. if a read operation is to be performed, any or all of these bits are set to a logic 0 level. all eight bits of the com- mand byte are transmitted to the econoram with a sep- arate time slot for each bit. read or write transaction read or write transactions are performed by initializing the econoram to a known state, issuing a command byte, and then generating the time slots to either read econoram contents or write new data. each transac- tion consists of 264 time slots. eight time slots transmit the command byte, the remaining 256 time slots trans- fer the data bits. (see figure 5.) once a transaction is started, it must be completed before a new transaction can begin. to initially set the econoram into a known state, 264 write zero time slots must be sent by the host. these write zero time slots will not corrupt the data in the eco- noram since a command byte has not been written. this operation will increment the address pointer inter- nal to the econoram to its maximum count value. upon reaching this maximum value, the econoram will ignore all additional write zero time slots issued to it and the internal address pointer will remain locked at the top count value. this condition is removed by the reception of a write one time slot, typically the first bit of a com- mand byte. once the econoram has been set into a known state, the command byte is transmitted to the econoram with eight write time slots. this resets the address pointer internal to the econoram and prepares it for the appropriate operation, either a read or a write. after the command byte has been received by the eco- noram, the host controls the transfer of data. in the case of a read transaction, the host issues 256 read time slots. in the case of a write transaction, the host issues 256 write time slots according to the data to be written. all data is read and written least significant bit first. although the ds2224 has the first 32 bits replaced by lasered rom rather than sram, it requires 256 write time slots for a complete write transaction. the data being sent during the first 32 write time slots has no effect on the ds2224 other than advancing the internal address pointer. as stated previously, it is not possible to change from read to write or vice versa before a trans- action is completed. downloaded from: http:///
ds2223/ds2224 080598 3/10 read/write timing diagram writeone time slot figure 1 60 m s t rec t low1 v pullup v pullup min v ih min v il max 0v 60 m s < t slot < 1 m s < t low1 < 15 m s 1 m s < t rec < 15 m s ds2223/ds2224 sampling window t slot writezero time slot figure 2 v pullup v pullup min v ih min v il max 0v t slot t rec t low0 60 m s < t low0 < t slot < 1 m s < t rec < ds2223/ds2224 sampling window 60 m s 15 m s readdata time slot figure 3 v pullup v pullup min v ih min v il max 0v t slot t rec t rdv t lowr 60 m s < t slot < 1 m s < t lowr < 15 m s 0 < t release < 45 m s 1 m s < t rec < t rdv = 15 m s t release host sampling window resistor master ds2223/ds2224 downloaded from: http:///
ds2223/ds2224 080598 4/10 command word figure 4 msb lsb w/r w/r w/r w/r w/r 001 all 1s write any 0 read select bits read/write transaction figure 5 read/write flow receive command word (reset address pointer) read/write data bit and is address pointer = 256? hold address pointer value, wait for new command word to reset address counter 264bit transaction 8 bits n y command word command word rom 224bit sram 256bit sram ds2223ds2224 lsb increment address pointer downloaded from: http:///
ds2223/ds2224 080598 5/10 typical current consumption vs. bit rate figure 6 10 m a 1 m a 100 na 10 na 5 na 129 pc/bit 4v @ +25 c 10 bps 100 bps 1 kbps 10 kbps 100 kbps bit rate current consumption typical leakage current vs. temperature figure 7 v cc = 4.0v 15.012.0 9.06.0 3.0 0.0 10 0 +10 +20 +30 +40 +50 +60 +70 temperature (deg. c) nanoamps leakage current downloaded from: http:///
ds2223/ds2224 080598 6/10 1wire interface the 1wire interface has only a single line by definition; it is important that host and econoram be able to drive it at the appropriate time. the econoram is an open drain part with an internal circuit equivalent to that shown in figure 8. the host can be the same equivalent circuit. if a bidirectional pin is not available, separate output and input pins can be tied together. the 1wire interface requires a pullup resistor with a value of approximately 5 k w to system v cc on the data signal line. the econoram has an internal opendrain driver with a 500 k w pulldown resistor to ground. the opendrain driver allows the econoram to be powered by a small standby energy source, such as a single 1.5 volt alkaline battery, and still have the ability to produce cmos/ttl output levels. the pulldown resistor holds the dq pin at ground when the econoram is not con- nected to the host. application examples econorams are extremely conservative with power. data can be retained in these small memories for as long as a month using the energy stored in a capacitor. data is retained as long as the voltage on the v cc pin of the econoram (v cap ) is at least 1.2 volts. a typical cir- cuit is shown in figure 9.when v cc is applied, capacitor c1 is charged and the econoram receives power directly from v cc . after power is removed, the diode cr1 prevents current from leaking back into the system, keeping the capacitor charged. in the standby mode, the econoram typically con- sumes only 12 na at 25 c. however, the powerdown process of the system can cause a slightly higher cur- rent drain. this is due to the fact that as system power ramps down, the signal attached to the dq pin of the econoram transitions slowly through the linear region, while the v cap voltage remains at its initial value. while in this region, the part draws more current as a function of the dq pin voltage (see figure 10). the data retention time can be estimated with the aid of figure 11. in this figure, the vertical axis represents the value of the capacitor c1; the horizontal axis is the data retention time in hours. the two curves represent initial v cap voltages of 3 and 5 volts. these curves are based on the assumption that the time the dq pin is in the lin- ear region is less than 100 ms. host to econoram interface figure 8 rxtx txrx open drain v cc 100 ohm mosfet host econoram 500 k w v cc 5 k w downloaded from: http:///
ds2223/ds2224 080598 7/10 suggested circuit figure 9 econo memory v cc dq gnd v cc v cap cr1 c1 + icc vs. dq voltage figure 10 v cc = +5v room temperature supply current <2 na dq pin voltage 0 1234 5 400200 0 supply current ( m a) downloaded from: http:///
ds2223/ds2224 080598 8/10 data retention time vs. capacitance figure 11 10k 1k 100 10 0 0.1 1 10 100 1k 10k time (hours) initial v cc voltage v cc = 3.0 v cc = 5.0 capacitance ( m f) using battery backup 14 mahr => 144 million transactions ds2223ds2224 + 31 2 data pin 1.5v eveready no. 321 downloaded from: http:///
ds2223/ds2224 080598 9/10 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +6.5v operating temperature 40 c to +85 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (40 c to +85 c) parameter symbol min typ max units notes data pin dq 0.5 6.0 v 1 supply voltage v cc 1.2 5.5 v 1 dc electrical characteristics (40 c to +85 c; v cc =2.0v to 5.5v) parameter symbol min typ max units notes input logic low v il 0.5 0.4 0.8 v 1 input logic high v ih v cc 0.5 6.0 v 1 sink current i l 1 2 ma 4 output logic low v ol 0.4 v 1 output logic high v oh v pup 5.5 v 1, 2 input resistance i r 500 k w 3 operating current i op 36 nc 5 standby current i stby 2 25 na 6 dc electrical characteristics (40 c to +85 c; v cc =1.4v 10%) parameter symbol min typ max units notes input logic low v il 0.5 0.2 v 1 input logic high v ih 1.0 6.0 v 1 sink current i l 1 2 ma 7 output logic low v ol 0.4 v 4 output logic high v oh v pup 5.5 v 1, 2 input resistance i r 500 k w 3 operating current i op 36 nc 5 standby current i stby 2 15 na 6 downloaded from: http:///
ds2223/ds2224 080598 10/10 ac electrical characteristics (40 c to +85 c; v cc =1.4v 10%) parameter symbol min typ max units notes time slot t slot 70 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 m s data setup time t su 1 m s 8 recovery time t rec 1 m s ac electrical characteristics (40 c to +85 c; v cc =2.0v to 5.5v) parameter symbol min typ max units notes time slot t slot 60 m s read data valid t rdv exactly 15 m s release time t release 0 15 45 m s write 1 low time t low1 1 15 m s write 0 low time t low0 60 m s data setup time t su 1 m s 8 recovery time t rec 1 m s notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage to system sypply. 3. input pulldown resistance to ground. 4. @ v ol =0.4v 5. 36 nanocoulombs per 264 time slots @ 1.5v (see figure 6). 6. see figure 7 for typical values over temperature. 7. @ v ol =0.2v 8. read data setup time refers to the time the host must pull the 1wire line low to read a bit. data is guaran- teed to be valid within 1 m s of this falling edge and will remain valid for 14 m s minimum (15 m s total from falling edge on the 1wire line). downloaded from: http:///
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